Since the late 1960's, a new generation of integrated circuits has been developed approximately every four years. Each generation has been characterized by a halving of device dimensions, resulting in a four-fold density increase over the preceding generation. Increases in circuit density have been consistently limited by the resolution of the available photolithographic equipment. The minimum size of features and spaces that a given piece of photolithographic equipment can produce is directly related to its resolution capability.
It has long been recognized, by those skilled in the fabrication of integrated circuits, that vertical film layers as thin as 0.01.mu. can be grown with a high degree of accuracy. Also, layers as thin as 0.1.mu. can be deposited by low pressure chemical vapor deposition, hereinafter known as LPCVD. By comparison, the minimum feature size, producible with the present generation of photolithography equipment used to produce 1-megabit SRAMs and 4-megabit DRAMs, is approximately 0.6.mu.. If deposition layers can be used to define horizontal dimensions within integrated circuits, the result will be increased circuit density.
Many die are typically fabricated on a singular semiconductor wafer. Complex circuitries are created on each die. Because of increasing device density on die, it is necessary to enhance the isolation of the different devices to ensure that no current flows through the substrate from one device to another. In FIG. 1, two active areas are isolated from each other by a field oxide region that has been thermally grown using a standard Locos process. During field oxide growth, patches of silicon nitride protect future active areas from oxidation. Electrical devices (e.g., transistors, resistors, capacitors) will ultimately be fabricated in the active areas. The oxide layer must be of relatively large width to ensure that there is no leakage current from one area to another. This leakage current is the result of what is termed bipolar latch up in the case where the two regions are of opposite types; that is, one is n type and the other is p type. Similar regions are also susceptible to leakage current.
In order to reduce the horizontal width of the oxide layer and maximize die space, trenches have been created via several processes. The trenches, filled with an insulative material such as silicon dioxide, extend into the substrate and act as insulating walls between active areas. Because trenches extend into the substrate, they can prevent bipolar latch up even though they may be narrower than the field oxide region of FIG. 1. In fact, the width can now be as narrow as present technology allows. FIG. 2 shows a trench manufactured with polycrystalline silicon deposited over an oxide region. The trench width is difficult to precisely predict when using this method due to variations in the polycrystalline silicon deposition. FIG. 3 depicts trench fabrication using an oxide mask created with a pitch doubling process that is the subject of a copending U.S. patent application submitted by Tyler Lowrey and Randal Chance of Micron Technology, Inc. and accorded Ser. No. 519,992, entitled "Method for Reducing, by a Factor of 2.sup.-N, the Minimum Masking Pitch of a Photolithographic Process Used in the Fabrication of an Integrated Circuit." In FIG. 4A an oxide mask is formed by under-etching the photoresist. Next, metal is sputtered onto the wafer. The photoresist shields a portion of the substrate next to the oxide mask from the metal. After the wafer has been sputtered, the metal covering the photoresist is lifted and the photoresist is etched producing a mask of metal and oxide for trench formation, FIG. 4B. There is a percentage of error in the predictability of trench size due to the nature of the sputtering process because of the unpredictable shielding effect of the photoresist. FIGS. 5A and 5B depict trench fabrication that is the subject of U.S. Pat. No. 4,502,914. This invention provides a structure of polymeric material with vertical sidewalls, the latter serving to make sidewall structures of silicon dioxide or nitride with dimensions in the sub-micrometer range. These sidewall structures can be used as masks directly. For the negative lithography, another layer is alternatively applied over the sidewall structures using a planarization which is partly removed until the peaks of the sidewall structures are exposed. Subsequently the sidewall structures themselves are removed. The resulting opening can then be used as a mask for trench formation. Providing uniformity of the planarization layer over the sidewall structures can be difficult using this method due to the fact that the sidewall structures can disrupt the flow of resist or other material during the spin.
Since the trenches are fabricated after the substrate has been exposed, the key to narrow, self-aligned isolation trenches is exposing a highly predictable narrow substrate region. The etch mask fabrication of the present embodiment facilitates even narrower, self-aligned trenches, with a minimum amount of masking steps using a deposition layer as a masking layer to precisely define the narrow spacing.